(1) Field of the Invention
This invention relates to a demultiplexer suitable for integration, and more particularly to a demultiplexer suitable for a high speed operation.
(2) Description of the Related Art
A demultiplexer suitable for a high speed operation is disclosed in Japanese Patent Laid-Open No. Hei 3-97329 (97329/91) wherein a plurality of basic circuits each in the form of a 1:2 demultiplexer circuit are combined to realize a 1:2.sup.N demultiplexer. FIG. 1 shows a logic circuit diagram of a conventional 8-bit demultiplexer as an example. Reference numeral 71 denotes a data input terminal, 72 a clock input terminal, reference numerals 73-1, 73-2, . . . and 73-8 denote data output terminals, 74-1 and 74-2 denote 1/2 clock signals, 75-1 and 75-2 denote 1/4 clock signals, 76-1 and 76-2 denote 1/8 clock signals, reference numeral 77 denotes a clock dividing circuit, 78 a master-slave D-type flipflop (hereinafter referred to as MS-DFF or further abbreviated as MS), and 79 a master-slave-master D-type flipflop (hereinafter referred to as MSM-DFF or further abbreviated as MSM).
Reference numeral 80 denotes a data input signal, reference numerals 81 and 82 denote demultiplexed signals demultiplexed to 1:2 from data input signal 80, 83 to 86 denote demultiplexed signals demultiplexed to 1:4 from data input signal 80, and 87 to 94 denote demultiplexed signal demultiplexed to 1:8 from data input signal 80.
An MSM-DFF is a flipflop including a current switch circuit connected in cascade connection to a conventional MS-DFF, and the output thereof is delayed by one half period of a clock signal as compared with the MS-DFF. The demultiplexer shown in FIG. 1 includes seven 1:2 demultiplexer circuits each having a basic construction including an MS-DFF and an MSM-DFF in pair and connected in a tree-like configuration to construct a 1:8 demultiplexer circuit.
Operation of the demultiplexer of FIG. 1 is described below with reference to a time chart shown in FIG. 2. First, an 8-bit multiplexed signal of data input signal 80 is latched as seen at signal 71' at a rising edge of clock signal 74-1 by the first stage MSM-DFF and then outputted at a falling edge of clock signal 74-1. Consequently, a demultiplexed signal is outputted for each odd-numbered bit as at signal 1, 3, 5, 7, . . . as seen from signal 81. Meanwhile, input signal 80 is latched at each rising edge of clock signal 74-2, which has a phase opposite to the phase of clock signal 74-1, by the first stage MS-DFF. Consequently, a demultiplexed signal is outputted for each even-numbered bit as at signal 2, 4, 6, 8, . . . as seen from signal 82. Thereafter, signal 81 is similarly demultiplexed for each 4 bits so as to obtain signals 1, 5, 1', 5', . . . indicated by signal 83 by one of the next stage MSM-DFFs and is demultiplexed for each 4 bits so as to obtain signals 3, 7, 3', 7', . . . indicated by signal 84 by one of the next stage MS-DFFs.
Then, thus demultiplexed 8-bit signals are outputted simultaneously. It is to be noted that the demultiplexed signals are outputted in accordance with their original time series of the original multiplexed signal from output signal terminals 73-1, 73-2, . . . and 73-8. In particular, the outputting order of the demultiplexed signals is defined such that the first bit in the time series is outputted to output terminal 73-1; the second bit is outputted to output terminal 73-2; . . . ; and the last bit in the time series is outputted to output terminal 73-8.
While the conventional demultiplexer can define the outputting order of demultiplexed signals, it is disadvantageous in that it cannot define output bits for the individual output terminals. In particular, since the first signal in a time series is not always the first bit in a frame constituted from 8 bits, it cannot be defined what numbered bit is outputted to output signal terminal 73-1. Therefore, in order to establish the condition wherein the first bit is outputted to output signal terminal 73-1, complicated post-processing must be applied to the outputs from the output signal terminals.
Further, the dividing circuit section of the 1:8 demultiplexer described as an example above requires, in order to prevent an error at any of the 1/2 division outputs, the 1/4 division outputs and the 1/8 division outputs, a reset circuit for uniquely deciding logic initial values for the individual outputs. Accordingly, the conventional demultiplexer is disadvantageous also in that the reset circuit has a bad influence upon a high speed operation.